High frequency field effect transistor with carrier extraction to reduce intrinsic conduction

ABSTRACT

A field effect transistor (FET) is of the type which employs base biasing to depress the intrinsic contribution to conduction and reduce leakage current. It incorporates four successive layers ( 102  to  108 ): a p +  InSb base layer ( 102 ), a  p   +  InAlSb barrier layer ( 104 ), a π intrinsic layer ( 106 ) and an insulating SiO 2  layer ( 108 ); p +  source and drain regions (110, 112) are implanted in the intrinsic layer ( 106 ). The FET is an enhancement mode MISFET ( 100 ) in which biasing establishes the FET channel in the intrinsic layer ( 106 ). The insulating layer ( 108 ) has a substantially flat surface supporting a gate contact ( 116 ). This avoids or reduces departures from channel straightness caused by intrusion of a gate groove, and enables a high value of current gain cut-off frequency to be obtained. In FETs with layers that are not flat, departures from channel straightness should not be more than 50 nm in extent, preferably less than 5 nm.

BACKGROUND OF THE INVENTION

[0001] The present application is a continuation-in-part of U.S.application Ser. No. 09/554,492 filed May 16, 2000, claiming priorityfrom PCT/GB98/01695 filed Jun. 10, 1996 claiming priority from UKapplication number GB9725189.6 filed Nov. 28, 1997, the subject matterof all of the recited priority documents herein incorporated byreference.

FIELD OF THE INVENTION

[0002] This invention relates to a field effect transistor (FET). Moreparticularly, although not exclusively, it relates to FETs such asMISFETs made from narrow bandgap semiconductor materials, ie bandgap EGin the region of or less than 0.5 eV. It is also relevant to FETs madefrom wider bandgap materials for use at elevated operating temperaturesabove ambient temperature.

DISCUSSION OF PRIOR ART

[0003] Narrow bandgap semiconductors such as indium antimonide (InSb)have useful properties such as very low electron effective mass, veryhigh electron mobility and high saturation velocity. These arepotentially of great interest for ultra high speed applications. InSb inparticular is a promising material for fast, very low power dissipationtransistors, because its electron mobility μ_(e) at low electric fieldsis nine times higher than that of GaAs and its saturation velocityv_(sat) is more than five times higher, despite GaAs having goodproperties in these respects. InSb is also predicted to have a largeballistic mean free path of over 0.5 μm. This suggests that InSb haspotential for high speed operation at very low voltages, allowing lowpower consumption, which would make it ideal for portable andhigh-density applications. Some of the properties of Silicon, GaAs andInSb at 295 K (ambient temperature) are compared in Table 1 as follows:TABLE 1 Properties of InSb at 295 K Parameter Silicon GaAs InSb UnitsE_(G) Bandgap 1.12 1.43  0.175 eV m*_(e) Electron 0.19 0.072 0.013 m₀Effective Mass μ_(e) Electron Mobility 1,500 8,500 78,000 cm²V⁻¹ s⁻¹ν_(sat) Saturation   1 × 10⁷    1 × 10⁷  >5 × 10⁷  cm s⁻¹ Velocity λ_(e)Electron Mean 0.04 0.15  0.58  μm Free Path n₁ Intrinsic Carrier 1.6 ×10¹⁰ 1.1 × 10⁷  1.9 × 10¹⁶ cm⁻³ Concentration

[0004] Until recently, the potentially valuable properties of InSb havebeen inaccessible at ambient temperatures due to its low band-gap andconsequently high intrinsic carrier concentration (˜2×10¹⁶ cm⁻³), whichis six and nine orders of magnitude above those of Si and GaAsrespectively. This leads to InSb devices exhibiting high leakagecurrents at normal operating temperatures at or near ambient temperatureof 295K, where the minority carrier concentration is much greater thanthe required value at normal doping levels. It was thought for manyyears that this was a fundamental problem which debarred InSb and othernarrow bandgap materials from use in devices at ambient temperature andabove. The problem was however overcome by means of the invention thesubject of U.S. Pat. No. 5,382,814, which discloses a non-equilibriummetal-insulator-semiconductor field effect transistor (MISFET) using thephenomena of carrier exclusion and extraction to reduce the intrinsiccontribution to the carrier concentration well below the equilibriumlevel. This prior art MISFET is a reverse-biased p⁺ p ⁺πn⁺ structure,where p denotes an InSb layer, p is a strained In¹⁻¹Al_(x)Sb layer(underlined p indicates wider band-gap than p), π indicates a weaklydoped p-type region that is intrinsic at ambient operating temperature,and the + superscript indicates a heavy dopant concentration; these fourlayers define three junctions between respective adjacent layer pairs,ie p⁺ p ⁺, p ⁺π and πn⁺ junctions respectively. The active region of thedevice is the π region, and minority carriers are removed from it at theπn⁺ junction acting as an extracting contact. The p ⁺π junction is anexcluding contact inhibiting re-introduction of these carriers. Inconsequence, under bias applied to the device the minority carrierconcentration falls, and the majority carrier concentration falls withit to preserve charge neutrality. This produces carrier concentrationsbelow intrinsic levels. A similar effect is produced by cooling. Herethe expression “intrinsic” is used with its normal construction to meanthat carriers arise largely from activation of valence states, andapproximately equal numbers of minority and majority carriers arepresent in the semiconductor material. This expression is sometimeswrongly used for extrinsic material (eg Si) to indicate simply that thedoping level is low, whereas in extrinsic material carriers ariselargely from activation of either donor or acceptor states and one typeof carrier (electrons or holes) predominates.

[0005] The device disclosed in U.S. Pat. No. 5,382,814 was a 1 μmrecessed-gate enhancement-mode MISFET structure. For investigationpurposes a variety of devices of this kind were produced. It waspredicted theoretically that the frequency f_(T) at which the currentgain would fall to unity in a device of this kind would be 55 GHz, butmeasured values were obtained which were only in the region of 10 GHz.The value of f_(T) is treated as a figure of merit by those skilled inthe art of high frequency transistors. The best value of f_(T) obtainedfor any of these devices was 17 GHz, despite attempts to limit devicecapacitance associated with overlap of gate contact metal on to sourceand drain regions. This indicates that it is difficult to realise thefull high frequency potential of InSb MISFETs.

SUMMARY OF THE INVENTION

[0006] It is an object of the invention to provide an alternative formof FET capable of exhibiting an improved value of current gain cut-offfrequency f_(T).

[0007] The present invention provides a field effect transistor (FET) ofthe kind including a region having intrinsic conductivity when unbiasedat an operating temperature of the FET and biasing means for depressingthe intrinsic contribution to the charge carrier concentration in theintrinsic region, characterised in that the FET also includes means fordefining a channel extending between a source region and a drain regionwith any intervening departure from channel straightness being not morethan 50 nm in extent, as appropriate to enable a high value of currentgain cut-off frequency to be obtained. Any such departure from channelstraightness is preferably not more than 5 nm in extent; the expression“extent” means the maximum height differential between any two regionsof the channel, eg its central region and a region adjacent to thesource or drain.

[0008] The invention provides the advantage that it is capable ofproviding greatly enhanced values of current gain cut-off frequencycompared to the prior art, indicating greatly improved high frequencyperformance. MISFETs in particular in accordance with the prior art werefound to have disappointing performance at high frequency much belowtheoretical expectations. The reason for this was originally notunderstood. However, a number of hypotheses were investigated in anattempt to resolve the problem. One of these hypotheses was thatover-etching a MISFET gate recess might degrade high frequencyperformance. Devices of the invention produced without an interveninggate groove intrusion have exhibited much better performance at highfrequency, and it is inferred that the hypothesis of the deleteriouseffect of gate grooving on performance is confirmed.

[0009] In one aspect, the FET of the invention is an enhancement modeMISFET; it may incorporate source and drain regions which are producedby introduction of heavy doping into a layer incorporating the intrinsicregion The source and drain regions may be produced by implantation,diffusion doping, alloying or introduction of damage. The intrinsicregion may be residually p-type doped and form extracting contact meanswith the source and drain regions, the channel formed in the intrinsicregion in response to bias being n-type.

[0010] In a preferred embodiment, the intrinsic region has an interfacewith a barrier region itself having an interface with a base region, andthe intrinsic, barrier and base regions (106, 104, 102) being of likeconductivity type and the barrier region being of relatively widerbandgap than the intrinsic and base regions and providing an excludingcontact to the intrinsic region.

[0011] The FET of the invention may include a gate contact insulatedfrom and extending at least over that part of the intrinsic regionbetween the source and drain regions to define an enhancement channeltherebetween in operation. The base region may be of p⁺ InSb with adopant concentration of at least 5×10¹⁷ cm⁻³; the barrier region may beof p ⁺ In_(1−x)Al_(x)Sb with x in the range 0.05 to 0.25 with a dopantconcentration of at least 5×10¹⁷ cm⁻³; the intrinsic region may be of πInSb with a dopant concentration of less than 5×10¹⁷ cm⁻³, preferably1×10¹⁵ cm⁻³ to 5×10¹⁶ cm⁻³ and the source and drain regions may be of n⁺InSb with a dopant concentration of at least 5×10¹⁷ cm⁻³.

[0012] The base, barrier and intrinsic regions are preferablysuccessively disposed in a layer structure, the source and drain regionsbeing produced by implantation, diffusion alloying or damage in theintrinsic region, and the intrinsic region preferably has asubstantially flat surface portion supporting a gate insulation layerand a gate contact.

[0013] In another aspect, the FET of the invention is a depletion modeMISFET having an associated channel region. It may incorporate sourceand drain regions which are heavily doped outgrowths formed upon eitherthe intrinsic region or the channel region; these regions mayalternatively be produced by implantation, diffusion, alloying orintroduction of damage. They may define therebetween a gate recessaccommodating a gate contact.

[0014] The intrinsic region may be p-type and either itself or thechannel region may form extracting contact means with the source anddrain regions.

[0015] In a preferred embodiment, the intrinsic region has an interfacewith a barrier region which itself has an interface with a base region,the intrinsic, barrier and base regions being of like conductivity typeand the barrier region being of relatively wider bandgap than theintrinsic and base regions and providing an excluding contact to theintrinsic region. In this embodiment:

[0016] the base region may be of p ⁺ InSb with at least 5×10¹⁷ acceptorscm⁻³;

[0017] the barrier region may be of p⁺In_(1−x)Al_(x)Sb with x in therange 0.05 to 0.25 and at least 5×10¹⁷ acceptors cm⁻³;

[0018] the intrinsic region is of π InSb with less than 5×10¹⁷ acceptorscm⁻³, preferably in the range 1×10¹⁵ cm⁻³ to 5×10¹⁶ cm⁻³; and

[0019] the source and drain regions are of n⁺ InSb with at least 5×10¹⁷donor cm³.

[0020] The intrinsic region may support a channel region, the base,barrier, intrinsic and channel regions being successively disposed in alayer structure, the source and drain regions being grown upon thechannel region and the channel region having a substantially flatsurface portion supporting a gate insulation layer and a gate contact.The source and drain regions may define therebetween a gate recess, thechannel region having a surface portion at an end of the recesssupporting the gate insulation layer and gate contact.

[0021] The channel region may lie between parts of the intrinsic region,the latter forming extracting contact means in combination with thesource and drain regions.

[0022] The base, barrier and intrinsic regions are preferablysuccessively disposed in a layer structure, the intrinsic regioncontaining the channel region and supporting the source and drainregions.

[0023] The biasing means for depressing the intrinsic contribution tothe carrier concentration in the intrinsic region is preferably arrangedto bias the FET at a point of infinite differential impedance where thevariation of gate threshold voltage due to substrate bias voltagevariations is minimised.

[0024] In an alternative aspect, the invention provides a method ofmaking an FET of the kind comprising biasing means for depressing theintrinsic contribution to the charge carrier concentration in anintrinsic region thereof, characterised in that the method includesdefining a channel extending between a source region and a drain regionsuch that any intervening departure from channel straightness is notmore than 50 nm in extent, as appropriate to enable a high value ofcurrent gain cut-off frequency to be obtained. Any such departure fromchannel straightness is preferably not more than 5 nm in extent.

BRIEF DESCRIPTION OF THE DRAWINGS

[0025] In order that the invention might be more fully understood,embodiments thereof will now be described, by way of example only, withreference to the accompanying drawings, in which:

[0026]FIG. 1 is a schematic sectional view of a prior art MISFET notdrawn to scale;

[0027]FIG. 2 shows a gate of the prior art MISFET of FIG. 1 on anexpanded scale;

[0028]FIG. 3 is a schematic sectional view of an n-channel enhancementmode MISFET of the invention (not drawn to scale) illustrated inidealised form with layers that are neither concave nor convex;

[0029]FIG. 4 is a schematic sectional view of a central region of ann-channel enhancement mode MISFET of the invention showing a minordegree of gate region concavity;

[0030]FIG. 5 is a band structure diagram for a reverse-biased p⁺ p ⁺πn⁺MISFET structure of the invention; it corresponds to a section on linesV-V in FIG. 3;

[0031]FIG. 6 graphically illustrates the output characteristic of theFIG. 3 MISFET;

[0032]FIG. 7 graphically illustrates the transfer characteristic of theFIG. 3 MISFET;

[0033]FIG. 8 illustrates the variation of current gain cut-off frequencywith gate length for the FIG. 3 MISFET and for similar modelled devices;

[0034]FIG. 9 illustrates the variation of AC gain parameters withfrequency for the FIG. 3 MISFET;

[0035]FIG. 10 is a schematic sectional view of an n-channel depletionmode MISFET of the invention (not drawn to scale);

[0036]FIG. 11 illustrates the variation of current gain cut-offfrequency f_(T) (GHz) as a function of gate length (μm) for a variety ofdevice technologies, both measured and modelled; and

[0037]FIG. 12 is a base current/voltage characteristic theoreticallyachievable for a MISFET of the kind in which carrier concentration isdepressed by exclusion and extraction.

DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS

[0038] Referring now to FIG. 1, there is shown a prior art MISFET 10 ofthe kind disclosed in U.S. Pat No. 5,382,814. The MISFET 10 consists oflayers of indium antimonide (InSb) and indium aluminium antimonide(In_(1−x)Al_(x)Sb). It has a substrate (not shown) supporting fourlayers of semiconductor material as follows: a heavily doped narrowbandgap p-type (p⁺) base layer 12, a relatively wide bandgap heavilydoped p-type (p ⁺) barrier layer 14, a lightly doped p-type (π) activelayer 16 and a heavily doped narrow bandgap n-type (n⁺) source/drainlayer 18. Layers 12, 16 and 18 are InSb and layer 14 isIn_(1−x)Al_(x)Sb. The π active layer 16 has predominantly intrinsicconductivity at 295K ambient temperature, whereas other layers 12, 14and 18 have predominantly extrinsic conductivity at this temperature.Interfaces between pairs of adjacent layers 12/14, 14/16 and 16/18 arep⁺ p ⁺, p ⁺π and πn⁺ junctions respectively, the first two of thesebeing heterojunctions and the last a homojunction. The p ⁺π and πn⁺junctions 14/16 and 16/18 are an excluding contact and an extractingcontact respectively.

[0039] The MISFET 10 has source and drain regions 20 and 22 withcontacts 24 and 26 respectively, the regions having an intervening gaterecess or groove 28 formed by etching through the n⁺ layer 18. Thebottom and sides of the gate depression are covered by a silicon oxidegate insulator 30 and a metal gate contact 32. It is necessary foroperation of the MISFET 10 that the recess 28 extend completely (oralmost completely) through the n⁺ layer 18 to avoid a short circuitbetween the source 20 and drain 22.

[0040] Carrier extraction and exclusion take place in the MISFET 10 whenbias is applied in normal operation. The layers 12 to 18 form a p⁺ p⁺πn⁺ diode which is reverse biased in operation, ie the base layer 12 isbiased negative with respect to the source region 20. Under this bias,the πn⁺ junction 16/18 acts as an extracting contact removing electrons(minority carriers) from the π layer 16. Such electrons cannot bereplenished from the p ⁺ barrier layer 14, because it acts incombination with the p⁺ base layer 12 as an excluding contact andprovides a potential barrier to electron flow to the π layer 16. Theelectron concentration in the π layer 16 therefore falls when the MISFET10 is biased, and with it the hole concentration in that layer forcharge neutrality reasons. This greatly reduces the conductivity in thelayer 16, which therefore reduces the leakage current between the source20 and drain 22.

[0041] As has been said, trial examples of the MISFET 10 have beenproduced which exhibited disappointing performance at high frequency.The theoretical value of the current gain cut-off frequency f_(T) (atwhich the current gain falls to unity) for these devices was 55 GHz, butmeasured values were only in the region of 10 GHz despite attempts tolimit device capacitance associated with overlap of gate metal on tosource and drain regions. The reason for this was not understood.However, a number of hypotheses were advanced and investigatedtheoretically in an attempt to identify a candidate artefact responsiblefor poor high frequency performance. One of these hypotheses wasassociated with the depth of the gate recess or groove. Theoreticalcalculations indicated that, if the gate recess was etched too deeply(which is difficult to control and measure), high frequency performancewould be degraded. The theoretical situation is illustrated in FIG. 2,in which the gate recess 28 is shown on an expanded scale.

[0042] For the MISFET 10 to be viable, the gate recess 28 must extendthrough most of—preferably entirely through—the n⁺ region 18 to avoid ashort circuit between source and drain; if this recess were to beover-etched it would continue down into the π region 16, and it ispostulated that an inverted step 34 was formed in the trial devices ofthe order of 100 nm in depth. If so, the MISFET channel (not shown)between source 20 and drain 22 would be U-shaped instead of straight asintended (in an enhancement mode MISFET the channel is formed under thegate electrode only in operation in response to application of bias).

[0043] To minimise the transit time of charge carriers between sourceand drain, the source-drain electric field should be directedlongitudinally of the channel, which is only possible in that part of aU-shaped channel extending parallel to this field. In such a channelthere would be regions in which the channel does not extend in thesource-drain direction and the source-drain electric field is thereforeinclined to the longitudinal channel direction; in consequence thelongitudinal field component would be weaker than would be the case ifthe field were parallel to this direction, which increases the transittime of charge carriers between source and drain as compared to the casewhere the field is entirely longitudinal. It is therefore deduced that aU-shaped channel would degrade f_(T) because the latter is related tothis transit time. If correct, this theoretical analysis implies that anetched gate recess should be avoided. This hypothesis was tested by theproduction of examples of the invention hereinafter set out.

[0044] Referring now to FIG. 3, an enhancement mode MISFET of theinvention is indicated generally by 100. It comprises a weakly dopedp-type InSb substrate (not shown) upon which are grown in successionfirst, second, third and fourth layers 102, 104, 106 and 108 having thefollowing thicknesses and compositions:

[0045] first (base) layer 102: p⁺ InSb 2 μm thick, Be dopantconcentration 3×10¹⁸ cm⁻³;

[0046] second (barrier) layer 104: p ⁺ In_(0.85)A_(0.15)Sb 20 nm thick,Be dopant concentration 3×10¹⁸ cm⁻³;

[0047] third (intrinsic) layer 106: π InSb 0.5 μm thick, Be dopantconcentration 1×10¹⁵ cm⁻³; and

[0048] fourth (insulating) layer 108: SiO₂ 70 nm thick.

[0049] More generally, suitable compositions for InSb/InAlSb FETs of theinvention are as follows:

[0050] base region: p⁺ InSb with an acceptor concentration of at least5×10¹⁷ cm⁻³;

[0051] barrier region: p ⁺ In_(1−x)Al_(x)Sb with x in the range 0.05 to0.25 and an acceptor concentration of at least 5×10¹⁷ cm⁻³; and

[0052] intrinsic region: π InSb with an acceptor concentration of lessthan 5×10¹⁷ cm⁻³, preferably in the range 1×10¹⁵ cm⁻³ to 5×10¹⁶ cm5⁻³.

[0053] The MISFET 100 may optionally include a buried p-type layer 109(indicated by chain lines) within the channel layer 106 to improveconfinement of charge carriers near the insulating layer 108. It has n⁺source and drain regions 110 and 112 each approximately 0.2 μm thickwith a neutral acceptor concentration of at least 5×10¹⁷ cm⁻³. It hassource, gate and drain contacts 114, 116 and 118 consisting ofsuccessive Cr and Au layers (not shown). The mesa length of the MISFET100 is 12 μm, this being its full width in the plane of the drawing. Ithas a mesa (and gate) width of 50 μm, this being the dimension extendingperpendicular to the plane of the drawing. The length of the gatecontact 116 (horizontal dimension in the plane of the drawing) wasnominally 0.7 μm; here “nominally” means that lithographic masks wereused of appropriate dimensions to produce the required length, but thelength was not measured. Other devices of similar construction and typewere also produced with nominal gate lengths in the range 0.7 to 2 μmand mesa width of 100 μm. The layers 102 to 108 were grown by molecularbeam epitaxy. The source and drain regions 110 and 112 were produced byion implantation using 70 keV S³² ions with a dose per unit area of5×10¹³ cm⁻². The ions were implanted through a native anodic oxide maskat an angle of 10° from the normal to the <110> direction in the crystalwith a substrate temperature of 100° C. This was followed by a rapidthermal anneal at 420° C. for 10 seconds with an Si₃N₄ cap to activatethe dopant and remove damage. Samples were then anodised and the oxidewas stripped off to remove damaged material before applying contacts.The process of producing the MISFET 100 can result in a minor degree ofconvexity of the layers 106 and 108, but it does not result in a heightdifferential of more than 50 nm between the central region of thechannel (when formed in response to gate bias voltage) and outer regionsof the channel adjacent the source and drain. The implantationestablished conducting paths permitting contact to the source and drainregions 110 and 112.

[0054] The fourth layer 108 consisted of 40 nm of sputtered SiO₂deposited on top of 30 nm of anodic oxide. Photolytic SiO₂ would havebeen preferable for the entire layer 108 but this was unavailable.

[0055] The gate contact 116 extends over the whole of that part of thethird or π layer 106 which is between the source and drain regions 110and 112, and overlaps these regions a little. Ideally, to minimisedevice capacitance the overlap would be zero, but in an enhancement modedevice it is important for the gate contact to extend fully betweenthese regions so that in operation the channel region can be establishedas required.

[0056] In the MISFET 100 the direct line between source and drainregions 110 and 112 is not significantly obscured by the geometry of thegate 116, certainly not to the extent of 100 nm experienced in the priorart device 10.

[0057]FIG. 3 is an idealised illustration, in that in practice an FET ofthe invention may have non-planar layers because of departures fromideal geometry caused by inaccuracies in the production process; ie theintrinsic region may be concave, convex or undulating so long as thisdoes not result in too severe a distortion of the channel. Concavity isillustrated in FIG. 4, in which parts equivalent to those described withreference to FIG. 3 are like-referenced with a suffix R. FIG. 4 shows acentral region 120 of an FET equivalent to the MISFET 100 except that itapproximates more closely to a practical device. It includes anintrinsic layer 106R, a gate insulation layer 108R and gate contact 116Rall of which are concave defining a V-shaped recess 122. The bottom ofthe recess 122 is defined by a vertex 124 at the centre of theinsulation layer 108R. The recess 122 has a depth indicated by H whichis not more than 50 nm. When the channel (not shown) is established inresponse to application of gate bias voltage, the recess 122 does notresult in a differential of more than 50 nm existing in the verticaldirection in the drawing between the central region of the channel (notshown) under the vertex 124 and outer regions of the channel adjacentthe source 110R and drain 112R; in other words any departure fromchannel straightness arising from gate region non-planarity will be lessthat 50 nm. Here the gate region is the upper part of the intrinsiclayer 106R adjacent the gate insulation layer 108R in which the channelis formed and which determines the channel shape. In other embodimentsof the invention it is the active region of the device accommodating thecentral region of the channel.

[0058] The recess depth H and any consequent departure from channelstraightness are preferably not more than 5 nm. In consequence, thechannel when established can extend substantially as determined by thesource, gate and drain voltages. As will be described later, this givesrise to greatly improved performance as compared to the prior art device10.

[0059]FIG. 5 provides a band structure diagram and associated chargecarrier densities in the MISFET 100 and as a function of verticaldistance x in μm measured from the lower edge of the first layer 102.The data given in this drawing are for a reverse-biased p⁺ p ⁺πn⁺structure; they relate to a vertical section through the MISFET 100 onlines V-V in FIG. 3 extending through the first (p⁺), second (p ⁺) andthird (π) layers 102, 104 and 106 and the (n⁺) source region 110. Theright hand ordinate is graduated in 1E+12 to 1E+19, which indicates 10¹²to 10¹⁹ cm³. The drawing shows the following variations, conduction andvalence band energies in graphs 140 and 142, net dopant concentration ingraph 144, and hole and electron concentrations in graphs 146 and 148respectively.

[0060] The intrinsic carrier concentration at 295K (ambient) in InSb is2×10¹⁶ cm⁻³. Graphs 146 and 148 show that in operation the actualcarrier concentrations are up to two orders of magnitude less than thisthroughout most of the active a region of the third layer 106, whichcorresponds to the approximately flat portion of graph 144. Thisdemonstrates that the carrier concentrations in the π region of thelayer 106 are being depressed by carrier exclusion and extractionarising respectively from the p ⁺π and πn⁺ junctions 104/106 and106/112.

[0061] The MISFET 100 was tested in a common-source configuration withthe base layer 102 biased to about −0.35 V relative to the source 114 toperform the carrier extraction; this voltage is defined as V_(bS) andcorresponds to the position of maximum dynamic resistance of the diodestructure provided by the base layer 102 and the source 110 or drain112. Drain and gate voltages of normal polarity were then applied, iethey were both biased positive relative to the source 110 apart from onecase where a small negative gate-source voltage was used.

[0062] The output characteristic of the MISFET 100 is shown in FIG. 6.It comprises nine graphs such as 160 and 162 indicating the variation ofdrain current I_(d) with drain voltage V_(ds) at constant gate voltageV_(gs) from −0.2 V to 1.4 V in steps of 0.2 V between adjacent graphs.It can be seen that the drain current starts to saturate at a drainvoltage of about 0.15 V, as indicated by a slight knee in each graph;this is a very low voltage for saturation to initiate, and it is duebroadly speaking to the electron mobility in InSb being very high. It isadvantageous because it implies that the MISFET 100 will have low powerrequirements. The output characteristic is generally of the classicalform for MISFETs, which is evidence that a viable MISFET has beenproduced. At a drain voltage V_(ds) of 0.3 V the drain current isswitchable between about 10 and 110 mAmm⁻¹ by changing the gate voltageV_(gs) from −0.2 to 1.2 V.

[0063] The transfer characteristic of the MISFET 100 is shown in FIG. 7.It comprises five graphs such as 160 and 162 indicating the variation oftransconductance g_(m) with gate voltage V_(gs) at constant gatevoltage. The gate voltage changes between adjacent graphs from 0.1 V to0.5 V in steps of 0.1 V. It can be seen that the maximum DCtransconductance of the MISFET 100 is about 120 mS mm¹, and thethreshold gate voltage is about 0.4 V.

[0064] The leakage pedestal of the MISFET 100 is about 8 mA mm⁻¹ asshown by the intercept on the current axis in FIG. 6. The maximum draincurrents are about 120 mA mm⁻¹, determined by the drain current ceasingto increase with gate voltage. The device starts to break down slowly ata drain voltage of around 0.5 V as indicated by the upward curvature ofthe current/voltage graphs at high drain voltage; this is due toband-to-band tunnelling and surface leakage (probably surface tunnellinggeneration), both of which it is possible to reduce. The MISFET 100 hada significant resistance in series with the channel, of about 2.5 Ohm oneach side, measured by forward biasing the base-source/drain diodes.This is believed mainly to be due to the contacting process, and willreduce the transconductances (and hence f_(T)) below ideal values.

[0065] The AC parameters of a number of enhancement mode MISFETs of theinvention with differing gate lengths were measured by the S-parametermethod with a drain voltage of 0.5 V, and the gate voltage was tuned formaximum S₂₁. Results were de-embedded from parasitic bond-padcapacitances using Koolen's method. FIG. 8 shows the measured maximumcurrent gain cut-off frequencies f_(T) as a function of gate length. Theresults follow a L_(G) ⁻² dependence, as indicated by a lower line 180;this is as would theoretically be expected if the velocity is notsaturated at pinch-off. Values of f_(T) as a function of gate lengthwere also calculated (modelled results) for these MISFETs, and indicatedby an upper line 182; they agree fairly well with the experimentalvalues, although they do show some effect of velocity saturation,presumably because the channel mobility used was higher. This suggeststhat further improvement is possible from reduced gate lengths.

[0066] The AC parameters of the MISFET 100 are shown in FIG. 9. Themeasured current gain cut-off frequency, f_(T), is 74 GHz—as far as isknown at present this is the highest f_(T) measured for any FET with 0.7μm gate length irrespective of transistor type or material. It is morethan a factor of four greater than the best value (17 GHz) obtained forany of prior art devices 10 produced for investigation purposes, andmore than a factor of seven greater than the typical value (10 GHz) forthese devices. It should be possible to increase f_(T) further byreducing the resistance in series with the channel. The frequencyf_(max) at which the unilateral power gain falls to unity is 89 GHz;this is limited by the channel series resistance, and by the outputconductance which is relatively low at present. It should therefore bepossible to achieve increased f_(max) in devices of the invention. Thesevalues for f_(T) and f_(max) represent a great improvement over theprior art, and it is inferred that they provide confirmation of thecorrectness of the hypothesis of the deleterious effect of gate groovingon performance of prior art devices.

[0067] The results obtained for devices of the invention were verypromising, and indicated the potential of the invention to providehigh-speed, low-power devices. Modelling—ie calculation—of devicecharacteristics was performed using ATLAS, a 2D drift-diffusion devicesimulator from Silvaco International, using published or measuredresults for InSb material parameters. The modelled results were testedagainst experimental p⁺ p ⁺πn⁺ diodes and prior art MISFETs, and foundto be in good agreement in terms of leakage currents, transconductanceand f_(T). Modelled results for an implanted enhancement-mode MISFETstructures similar to that shown in FIG. 3 but with gate lengths of 1 μmand 0.25 μm are shown in the following Table 3, which providestheoretically attainable values for maximum g_(m), f_(T) and f_(max).The values for 0.25 μm gate length assume the gate insulator oxidethickness to be scaled by the same factor as the gate length. TABLE 2Modelled Parameters for Enhancement-mode MISFETs of the Invention GateLength 1.0 μm 0.25 μm Maximum g_(m) 188 mS mm⁻¹ 500 mS mm⁻¹ Current GainCut-off Frequency ƒ_(T) 68 GHz 185 GHz Unity Unilateral Power Gain 202GHz 264 GHz Frequency ƒ_(max)

[0068] These maximum transconductance values represent a considerableimprovement on that of 25 mS mm⁻¹ quoted for the prior art device ofU.S. Pat. No. 5,382,814.

[0069] The MISFET 100 is an InSb/In_(1−x)Al_(x)Sb heterostructure. Thereare a number of other semiconductor material combinations that aresuitable for construction of devices of the invention. Two semiconductormaterials are required with differing bandgaps, but they need not belattice matched. The lesser bandgap should be sufficiently narrow thatit is possible to purify the material enough to exhibit predominantlyintrinsic conductivity at the FET operating temperature (impossible withSi at the present time); this implies a bandgap which is in the regionof or less than 0.5 eV for a device operating at ambient temperature of295K, but materials of greater bandgap may be used for elevatedoperating temperatures.

[0070] Combinations of materials that may be used to produce FETs of theinvention include PbSe/PbS, In_(1−y)Al_(y)Sb/In_(1−x)Al_(x)Sb,InAs/InAs_(1−x)P_(x), InAs_(1−x)Sb_(x)/In_(1−y)Al_(y)Sb,InAs_(1−x)Sb_(x)/InAs_(1−y)P_(y), GaAs/Ga_(1−x)Al_(x)As,In_(1−x)Ga_(x)Sb/In_(1−y)Al_(y)Sb and Hg_(1−x)Cd_(x)Te/Hg_(1−y)Cd_(y)Te.Values of the composition parameters x, or x and y must be suitablychosen. The MISFET consisted of InSb/In_(1−x)Al_(x)Sb, which is aspecial case of the second of these with the parameter y equal to zero.

[0071] Referring now to FIG. 10, a depletion mode MISFET of theinvention is indicated generally by 200. It comprises a weakly dopedp-type InSb substrate (not shown) upon which are grown five successivelayers 202, 204, 206, 208 and 210 having the following thicknesses andcomposition:

[0072] first (base) layer 202: p⁺ InSb 2 μm thick, Be dopantconcentration 3×10¹⁸ cm⁻³;

[0073] second (barrier) layer 204: p ⁺ In_(0.85)Al_(0.15)Sb 20 nm thick,Be dopant concentration 3×10¹⁸ cm⁻³;

[0074] third (intrinsic) layer 206: πInSb 0.5 μm thick, Be dopantconcentration 1×10¹⁵ cm⁻³; and

[0075] fourth (channel) layer 208: p InSb 20 nm thick, Si dopantconcentration 3×10¹⁷ cm⁻³;

[0076] fifth (gate insulation) layer 210: SiO₂ 70 nm thick.

[0077] The MISFET 200 may optionally include a buried p-type layer 211(indicated by chain lines) within the intrinsic layer 206 to improveconfinement of charge carriers near the gate insulation layer 210. Ithas n⁺ source and drain regions 212 and 214 each approximately 0.2 μmthick with an Si dopant concentration of 2×10¹⁸ cm⁻³ and formingextracting contacts to the channel layer 208. These regions providecarrier extraction in the intrinsic layer 206 via the channel layer 208.The MISFET 200 has source, gate and drain contacts 216, 218 and 220consisting of successive Cr and Au layers (not shown). Except whereindicated above, the MISFET 200 has dimensions similar to theenhancement mode device described earlier. It has a mesa length 12 μm, amesa (and gate) width of 50 μm and gate contact length nominally 0.7 μm.The layers 202 to 208 were grown by molecular beam epitaxy (MBE). Thesource and drain regions 212 and 214 were produced by MBE growth on thechannel layer 208, the central region of the latter being masked toavoid growth upon it. After removal of this mask, the gate insulationlayer 210 and electrode 218 are deposited. The source and drain regions212 and 214 define between them a gate recess 222 within which the gateinsulation layer 210 and gate contact 218 are located supported by thechannel layer 208. The recess may be more or less deep than the heightof the gate electrode 218. It is important to note that the gate recess222 is not a groove produced by etching as in the prior art, but insteada recess defined by growth of upstanding sides. In consequence theformation of the recess 222 does not imply problems associated with toodeep a groove affecting channel shape.

[0078] The fifth layer 210 consisted of 40 nm of sputtered SiO₂deposited on top of 30 nm of anodic oxide. The gate contact 218 extendsover most of that part of the channel layer 208 which is between thesource and drain regions 212 and 214; the degree to which it does thisis not very critical because it is merely required formodulation/depletion of an existing device channel, as opposed toestablishment of a complete channel between source and drain which isrequired in an enhancement mode device.

[0079] The MISFET 200 employs a channel layer 208 to provide anaccessible source of electrons; the latter in turn provides a conductingpath from source 212 to drain 214 depletable of charge carriers by thegate electrode potential. This path may be entirely within the channellayer 208 or the intrinsic layer 206 or may be partly in one of theseand partly in the other. The threshold voltage of the MISFET 200 isdetermined by the doping per unit area of the channel layer 208, ie theproduct of the layer thickness and its doping per unit volume. Thechannel layer 208 extends substantially along the direction of theelectric field produced by the source-drain voltage in the absence of agate voltage. This layer is not U-shaped to any unacceptable degree; ieany concavity or convexity in this layer is less than 50 nm in extent.

[0080] Modelled—ie theoretical—performance figures were obtained for thedepletion-mode MISFET 200 assuming that the gate insulation oxidethickness was equal to that in the device 100. These figures are shownin Table 3 as follows: TABLE 3 Modelled Parameters for Depletion-modeMISFETs of the Invention Gate Length 1.0 μm 0.25 μm Maximum g_(m) 190 mSmm⁻¹ 590 mS mm⁻¹ Current Gain Cut-off Frequency ƒ_(T) 68 GHz 220 GHzUnity Unilateral Power Gain 164 GHz 377 GHz Frequency ƒ_(max)

[0081] Referring to now to FIG. 11, current gain cut-off frequency f_(T)(GHz) is shown as a f+unction of gate length (μm) for a variety ofdevice technologies, actual or modelled, as follows: InSbideal—(calculated from gate length and carrier velocity only), modelledInSb enhancement and depletion mode MISFETs, the InSb enhancement modeMISFET 100 InP—and GaAs-based HEMTs and silicon NMOS.

[0082] It can be seen that the Table 2 results for f_(T) in the MISFET100 are only slightly below the ideal trend-line in FIG. 11, with aslight tailing off due to the overlap capacitance from the source anddrain implants. These results should be attainable with improvedperformance from the implanted diodes, reduced series resistance andpatterning of the gate oxide to reduce overlap capacitance. Comparisonof the Table 3 results for f_(T) in the MISFET 200 with FIG. 11 indicatethat this depletion-mode device does not suffer from the saturationeffect seen in the enhancement-mode devices such as the MISFET 100 andthis is attributed to the former having lower input capacitance.

[0083] The MISFET 200 may have a different form of channel. The 20 nmthick channel layer 208 may be replaced by a 3 nm thick InSb channellayer with a Si dopant concentration of 2×10¹⁸ cm⁻³ separated from thegate oxide layer 210 by a π InSb layer 20 nm thick with a dopantconcentration of 1×10¹⁵ cm⁻³. This is equivalent to the channel layerbeing reduced in thickness and buried in the intrinsic π layer 206, andis estimated to give a 30% operating speed enhancement. In this case thesource and drain regions 212 and 214 form extracting contacts with theintrinsic layer 206.

[0084] Referring now to FIG. 12, there is shown a base current/voltageI_(B)V_(BS) characteristic 250 which is theoretically achievable by aMISFET of the kind in which carrier concentration is depressed byexclusion and extraction. Here the base current is that flowing betweena base layer and a source region. This current is not for the purposesof biasing the MISFET source, gate and drain relative to one another.Instead it is for the purposes of reducing the carrier concentration andleakage current in the intrinsic device region. The characteristic 250corresponds to a device containing a lower Shockley/Read trap densitythan is currently attainable. The device is a p⁺ p ⁺πn⁺ diode structurewhich is reverse biased in operation, ie it has a base layer which isbiased negative with respect to its source region. Under this bias,carrier extraction and exclusion take place in the intrinsic layer, fromwhich electrons (minority carriers) are removed by an associated πn⁺junction acting as an extracting contact.

[0085] At a point 252, the slope of the I_(B)V_(BS) characteristic 250is zero, indicating infinite differential impedance. At this point, thevariation of gate threshold voltage with base bias voltageV_(BS)—referred to as “back gating”—is minimised, and so this is thepreferred operating point for base bias.

[0086] The modelled results referred to above come from drift-diffusionsimulation and neglect ballistic effects, which are expected to becomesignificant at gate lengths of around 0.5 μm. The effect of this will beto increase the average saturation velocity, and hence the g_(m) andf_(T) leading to potential for greater improvements in performance.

[0087] Transistors of the invention are potentially applicable tohigh-speed analogue device applications. If grown on a semi-insulatingsubstrate or virtual substrate, they could be used in microwaveintegrated circuits. An InSb device is operative at low voltage, lessthan 0.5 V, and is therefore characterised by low power consumptionwhich is extremely useful for hand-held applications, providing longerbattery lifetimes. Also, it has high electron velocity which allowshigher ultimate frequencies to be reached, or alternatively provides therequired operating speed at a longer gate length, making it more robust.Transistors of the invention may also be used as digital devices,especially for low-complexity circuits. They are very attractive forhigh-speed low-power applications because they potentially have a verylow Pτ product, where P is energy dissipated in a switching operationand τ is the time to switch.

[0088] The invention provides FETs which are fast, have low powerdissipation and exploit the inherent high electron mobility andsaturation velocity of InSb/In_(1−x)Al_(x)Sb. These FETs givehigh-speed, low-power performance and demonstrate off-state leakagecurrents which are well below levels normally associated withInSb/In_(1−x)Al_(x)Sb, due to the incorporation of carrier exclusion andextraction techniques. MISFETs of the invention with 0.7 μm gate lengthhave the highest f_(T) value yet reported for this gate length, andfurther improvements in both speed and off-state leakage are expected tobe obtainable.

1. A field effect transistor (FET) of the kind including a region (106)having intrinsic conductivity when unbiased at an operating temperatureof the FET and biasing means for depressing the intrinsic contributionto the charge carrier concentration in the intrinsic region (106),further including means for defining a channel extending between asource region (110) and a drain region (112) with any interveningdeparture from channel straightness being not more than 50 nm in extent,as appropriate to enable a high value of current gain cut-off frequencyto be obtained.
 2. An FET according to claim 1 wherein any departurefrom channel straightness is not more than 5 nm in extent.
 3. An FETaccording to claim 1, wherein the FET is an enhancement mode MISFET(100).
 4. An FET according to claim 1, wherein the FET incorporatessource and drain regions (110, 112) which are heavily doped n-type. 5.An FET according to claim 1, wherein the intrinsic region (106) isp-type and forms extracting contact means in combination with the sourceand drain regions (110, 112).
 6. A field effect transistor (FET) of thekind including a region (106) having intrinsic conductivity whenunbiased at an operating temperature of the FET and biasing means fordepressing the intrinsic contribution to the charge carrierconcentration in the intrinsic region (106), further including means fordefining a channel extending between a source region (110) and a drainregion (112) with any intervening departure from channel straightnessbeing not more than 50 nm in extent, as appropriate to enable a highvalue of current gain cut-off frequency to be obtained, wherein theintrinsic region (106) has an interface with a barrier region (104)itself having an interface with a base region (102), and wherein theintrinsic, barrier and base regions (106, 104, 102) are of likeconductivity type and the barrier region (104) is of relatively widerbandgap than the intrinsic and base regions (106, 102) and provides anexcluding contact to the intrinsic region (106).
 7. An FET according toclaim 6, further including a gate contact (116) insulated from andextending at least over that part of the intrinsic region (106) betweenthe source and drain regions (110, 112) to define an enhancement channeltherebetween in operation.
 8. An FET according to claim 6 wherein: a)the base region (102) is of p⁺ InSb and has an acceptor concentration ofat least 5×10 cm⁻³; b) the barrier region (104) is of p ⁺In_(1−x)Al_(x)Sb with x in the range 0.05 to 0.25 and has an acceptorconcentration of at least 5×10¹⁷ cm⁻³; c) the intrinsic region (106) isof π InSb with an acceptor concentration of less than 5×10¹⁷ cm⁻³,preferably in the range 1×10¹⁵ cm⁻³ to 5×10¹⁶ cm⁻³; and d) the sourceand drain regions (110, 112) are of n⁺ InSb with a dopant concentrationof at least 5×10¹⁷ cm⁻³.
 9. A FET according to claim 5, wherein thebase, barrier and intrinsic regions (102, 104, 106) are successivelydisposed in a layer structure, and the intrinsic region (106) has asubstantially flat surface portion supporting a gate insulation layer(108) and a gate contact (116).
 10. A field effect transistor (FET) ofthe kind including a region (106) having intrinsic conductivity whenunbiased at an operating temperature of the FET and biasing means fordepressing the intrinsic contribution to the charge carrierconcentration in the intrinsic region (106), further including means fordefining a channel extending between a source region (110) and a drainregion (112) with any intervening departure from channel straightnessbeing not more than 50 nm in extent, as appropriate to enable a highvalue of current gain cut-off frequency to be obtained, wherein the FETis a depletion mode MISFET (200) having an associated channel region(208).
 11. An FET according to claim 10, wherein the FET incorporatessource and drain regions (212, 214) which are heavily doped outgrowthsformed upon either the intrinsic region (206) or the channel region(208), the outgrowths defining therebetween a gate recess (222)accommodating a gate contact (218).
 12. An FET according to claim 10,wherein the intrinsic region (206) is p-type and either itself or thechannel region (208) forms extracting contact means with the source anddrain regions (212, 214).
 13. An FET according to claim 10, wherein theintrinsic region (206) has an interface with a barrier region (204)which itself has an interface with a base region (102), and wherein theintrinsic, barrier and base regions (206, 204, 202) are of likeconductivity type and the barrier region (204) is of relatively widerbandgap than the intrinsic and base regions (206, 202) and provides anexcluding contact to the intrinsic region (206).
 14. An FET according toclaim 13, wherein: a) the base region (102) is of p⁺ InSb and has anacceptor concentration of at least 5×10¹⁷ cm⁻³; b) the barrier region(104) is of p ⁺ In_(1−x)Al_(x)Sb with x in the range 0.05 to 0.25 andhas an acceptor concentration of at least 5×10¹⁷ cm⁻³; c) the intrinsicregion (106) is of π InSb with an acceptor concentration of less than5×10¹⁷ cm³, preferably in the range 1×10¹⁵ cm³ to 5×10¹⁶ cm³; and d) thesource and drain regions (110, 112) are of n⁺ InSb with a donorconcentration of at least 5×10¹⁷ cm⁻³.
 15. A FET according to claim 13,wherein the intrinsic region (206) supports a channel region (208), thebase, barrier, intrinsic and channel regions (202, 204, 206, 208) aresuccessively disposed in a layer structure, the source and drain regions(212, 214) are grown upon the channel region (208) and the channelregion (208) has a substantially flat surface portion supporting a gateinsulation layer (210) and a gate contact (218).
 16. An FET according toclaim 15, wherein the source and drain regions (212, 214) definetherebetween a gate recess (222), the channel region (208) has a surfaceportion at an end of the recess (222) supporting a gate insulation layer(208) and a gate contact (210).
 17. An FET according to claim 10,wherein the channel region lies between parts of the intrinsic regionand the latter forms extracting contact means in combination with thesource and drain regions (212, 214).
 18. An FET according to claim 17,wherein the base, barrier and intrinsic regions (202, 204, 208) aresuccessively disposed in a layer structure, the intrinsic region (206)contains the channel region (208), the source and drain regions (212,214) are supported by the intrinsic region (206) and define therebetweena gate recess (222), and the intrinsic region (206) has a surfaceportion at an end of the recess (222) supporting a gate insulation layer(208) and a gate contact (210).
 19. A field effect transistor (FET) ofthe kind including a region (106) having intrinsic conductivity whenunbiased at an operating temperature of the FET and biasing means fordepressing the intrinsic contribution to the charge carrierconcentration in the intrinsic region (106), further including means fordefining a channel extending between a source region (110) and a drainregion (112) with any intervening departure from channel straightnessbeing not more than 50 nm in extent, as appropriate to enable a highvalue of current gain cut-off frequency to be obtained, wherein thebiasing means for depressing the intrinsic contribution to the chargecarrier concentration in the intrinsic region (106, 206) is arranged tobias the FET (100, 200) at a point of infinite differential impedancewhere the variation of gate threshold voltage with substrate biasvoltage variations is minimised.
 20. A method of making an FET of thekind comprising biasing means for depressing the intrinsic contributionto the charge carrier concentration in an intrinsic region (106)thereof, said method including the step of defining a channel extendingbetween a source region (110) and a drain region (112) such that anyintervening departure from channel straightness is not more than 50 nmin extent, as appropriate to enable a high value of current gain cut-offfrequency to be obtained.
 21. A method of making an FET according toclaim 20, wherein any departure from channel straightness is not morethan 5 nm in extent.